In recent years, since variation in delays of an element and wiring has increased due to miniaturization, it has become more difficult to perform a timing design of an integrated circuit.
Even though same elements and wirings in terms of design are used, variation in characteristic values such as a size and impurity concentration occurs between elements and wirings mounted on different chips at a time of manufacturing. As a result, variation occurs in delay values (delay times) of the elements and wirings.
In conventional timing design methods, a maximum delay value and a minimum delay value within a range of variation among such elements and wirings are used, and a maximum value and a minimum value of a circuit delay (i.e. a delay time per circuit) are calculated from the maximum delay value and the minimum delay value of elements and wirings in the circuit.
Then, a variation of a circuit delay is equal to an accumulation of variations of elements and wirings.
Patent Document 1:
Japanese Patent Kokai Publication No. JP-P2002-222232A
Patent Document 2:
Japanese Patent Kokai Publication No. JP-P2006-277359A
Non-Patent Document 1:
Sparso, J., Furber, S., “Principles of Asynchronous Circuit Design,” Kluwer Academic Publishers, 2001, pp. 16-27